From 55cf9f17ce5e026f029fe798d7514e42a4c31059 Mon Sep 17 00:00:00 2001 From: "kaf24@firebug.cl.cam.ac.uk" Date: Fri, 20 May 2005 22:28:12 +0000 Subject: [PATCH] bitkeeper revision 1.1494 (428e647cwMGQpFEvYX5LZ0S3SXAZVQ) Read VMX configuration details from architectural registers. Signed-off-by: Nitin Kamble Signed-off-by: Jun Nakajima Signed-off-by: Keir Fraser --- xen/arch/x86/vmx.c | 16 ++++++++++++++-- xen/arch/x86/vmx_vmcs.c | 6 ++++-- xen/include/asm-x86/msr.h | 6 ++++++ xen/include/asm-x86/vmx_vmcs.h | 1 - 4 files changed, 24 insertions(+), 5 deletions(-) diff --git a/xen/arch/x86/vmx.c b/xen/arch/x86/vmx.c index 6b296bb8e9..fecc98f791 100644 --- a/xen/arch/x86/vmx.c +++ b/xen/arch/x86/vmx.c @@ -51,10 +51,10 @@ void do_nmi(struct cpu_user_regs *, unsigned long); int start_vmx() { struct vmcs_struct *vmcs; - unsigned long ecx; + u32 ecx; + u32 eax, edx; u64 phys_vmcs; /* debugging */ - vmcs_size = VMCS_SIZE; /* * Xen does not fill x86_capability words except 0. */ @@ -63,6 +63,18 @@ int start_vmx() if (!(test_bit(X86_FEATURE_VMXE, &boot_cpu_data.x86_capability))) return 0; + + rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx); + + if (eax & IA32_FEATURE_CONTROL_MSR_LOCK) { + if ((eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) == 0x0) { + printk("VMX disabled by Feature Control MSR.\n"); + return 0; + } + } + else + wrmsr(IA32_FEATURE_CONTROL_MSR, + IA32_FEATURE_CONTROL_MSR_LOCK | IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0); set_in_cr4(X86_CR4_VMXE); /* Enable VMXE */ diff --git a/xen/arch/x86/vmx_vmcs.c b/xen/arch/x86/vmx_vmcs.c index b4906bf905..e840c4c3d0 100644 --- a/xen/arch/x86/vmx_vmcs.c +++ b/xen/arch/x86/vmx_vmcs.c @@ -37,12 +37,14 @@ struct vmcs_struct *alloc_vmcs(void) { struct vmcs_struct *vmcs; - unsigned int cpu_sig = cpuid_eax(0x00000001); + u32 vmx_msr_low, vmx_msr_high; + rdmsr(MSR_IA32_VMX_BASIC_MSR, vmx_msr_low, vmx_msr_high); + vmcs_size = vmx_msr_high & 0x1fff; vmcs = (struct vmcs_struct *) alloc_xenheap_pages(get_order(vmcs_size)); memset((char *) vmcs, 0, vmcs_size); /* don't remove this */ - vmcs->vmcs_revision_id = (cpu_sig > 0xf41)? 3 : 1; + vmcs->vmcs_revision_id = vmx_msr_low; return vmcs; } diff --git a/xen/include/asm-x86/msr.h b/xen/include/asm-x86/msr.h index 5eeda436a7..e576613c13 100644 --- a/xen/include/asm-x86/msr.h +++ b/xen/include/asm-x86/msr.h @@ -79,6 +79,12 @@ #define MSR_IA32_PLATFORM_ID 0x17 #define MSR_IA32_EBL_CR_POWERON 0x2a +/* MSRs & bits used for VMX enabling */ +#define MSR_IA32_VMX_BASIC_MSR 0x480 +#define IA32_FEATURE_CONTROL_MSR 0x3a +#define IA32_FEATURE_CONTROL_MSR_LOCK 0x1 +#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON 0x4 + /* AMD/K8 specific MSRs */ #define MSR_EFER 0xc0000080 /* extended feature register */ #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ diff --git a/xen/include/asm-x86/vmx_vmcs.h b/xen/include/asm-x86/vmx_vmcs.h index 1a39bb7a02..5fe27f002e 100644 --- a/xen/include/asm-x86/vmx_vmcs.h +++ b/xen/include/asm-x86/vmx_vmcs.h @@ -31,7 +31,6 @@ void vmx_enter_scheduler(void); #define VMX_CPU_STATE_PG_ENABLED 0 #define VMX_CPU_STATE_ASSIST_ENABLED 1 -#define VMCS_SIZE 0x1000 struct vmcs_struct { u32 vmcs_revision_id; -- 2.30.2